In fabrication of an FET, such as an FET with a T-shape short gate electrode and an FET with a heterojunction, a reflow process is performed in order to improve the quality of those FETs. The reflow process is performed to an insulating layer, for example, to avoid breaking of the gate electrode, and to improve the uniformity of etching with a fine pattern.
Conventional methods for fabricating an FET are, for example, described in Japanese Patent Publications, Koukoku, H8-15161 and Laying Open, Kokai, H5-160019. According to a method described in Koukoku H8-15161, a first resist layer is formed on a semiconductor substrate to have a first gate opening. Then, the semiconductor substrate is etched at the bottom of the first gate opening to have a recess-etching surface, and the first resist layer is removed. Next, an insulating layer is formed over the entire surface of the structure, and a second resist layer is formed on the insulating layer to have a second gate opening. Then, a reflow-process is performed to the second resist layer to have a curved surface, and the insulating layer is removed at the bottom of the second gate opening. After that, a metal layer is formed in the second gate opening, and the second resist layer is removed to form a gate electrode.
According to the conventional method, the insulating layer is removed after the reflow-process, and therefore, the gate length (channel length) may be changed during the step of removing the insulating layer. As a result, the pattern shift varies, and therefore, the characteristics of the semiconductor device may be varied. Such a problem are occurred as well in the conventional method shown in Kokai H5-160019. The pattern shift means the difference in size between the original gate pattern and the actual gate length. In general, the pattern shift occurs in every kind of etching process. In fabrication of a gate electrode, however, it is required to make the pattern shift consistent to control the size of gate length precisely.